1. Field of the Invention
This invention relates to a fabrication method for a vertical metal oxide semiconductor (MOS) transistor. More particularly, the invention relates to a fabrication method for a MOS transistor comprising a vertical channel.
2. Description of the Related Art
In the design for the very large scale integration (VLSI), the dimensions for the transistor device are continuously being reduced to increase the integration. A critical point in the manufacturing of a transistor with small dimension is the reduction of the channel length. To effectively reduce the channel length of a MOS transistor is a very important issue.
Conventionally, the channel length is defined by the photolithography technique. The current photolithography technique development, however, is limited by, for example, the wavelength of the light source, the material and thickness of the photoresist layer, the scattering and deflection properties of light. For the manufacturing of a line width of 0.25 micron and below, it is, therefore, difficult to control the channel length by means of photolithography.
Comparing to the photolithography technique, the development of the thin film deposition and the ion implantation technology are more advance, for example, chemical vapor deposition (CVD) can accurately control the thickness of the deposited thin film to a few angstrom.